1. Field of the Invention
The invention relates to the phase change memory, and more particularly to the reference memory unit of the phase change memory.
2. Description of the Related Art
With the growth in the use of portable electronic devices, demand for non-volatile memory has increased. Among all kinds of emerging non-volatile memories, phase change memory is the most promising candidate for the next generation non-volatile memory due to its higher speed, lower power consumption, higher capacity, reliability, easier process integration and lower cost.
Phase change memory is based on the fast and reversible phase transitions of chalcogenide alloy which result in a highly resistive amorphous state and low resistive crystalline state, i.e. the logic data of 1 and 0. Thus, an adequate read circuit is desirable for correctly and reliably sensing the programmed data of the phase change memory. Typically a memory system comprises a reference memory array and a primary memory array. The unit cells in the reference memory array generate reference signals which are different from the signals generated by the programmed bits in the primary memory array. The read circuit is thus used to compare the reference signals with the signals from the primary memory array such that the programmed data in the primary memory array can be identified. To avoid a wrong sensing of the programmed state due to the reference signal error, it is important to develop an ideal reference memory array.
The ideal reference memory array must have the characteristics: (1) easy implementation without additional processes or complicated circuit design; (2) high reliability and stability, i.e. the reference memory array has a high tolerance to the memory state variation of the phase change memory; (3) flexibility and compatibility with memory array.
FIG. 1 is a schematic diagram of a conventional memory array with a parallel-connected reference memory array announced by Ovonyx Inc. in 2001. The phase change memory 100 comprises a primary memory array, columns C1 to C4, a reference memory array 130, columns C5 and C6, and a comparison circuit 140. The primary memory array 120 comprises a plurality of the memory units 121 and the reference memory array 130 comprises a plurality of reference memory units 131, wherein the memory units 121 and the reference memory unit 131 have the same structure. When the phase change memory 100 is accessed, the primary memory array 120 provides sensing signals SSE1 to SSE4 corresponding to the memory states and the reference memory array 130 provides a reference signal SRE. The comparison circuit 140 then compares the signals SSE1 to SSE4 with the signal SRE to identify the data stored in the phase change memory 100. In the conventional memory architecture, the reference memory array 130 is implemented by two columns, C5 and C6, parallel connected to the primary memory array 120. The memory units 121 of the primary memory array 120 and the reference memory unit 131 of the reference memory array 130 have the same structure. According to this architecture, however, the reference signal SRE generated by the conventional reference memory array 130 is nest easily adjustable and the reference signal SRE may drift due to process variation. In other words, the reference signal SRE may mix with the sensing signal SSE corresponding to a specific memory state, thus easily leading to a sensing deviation.
Assuming that the memory unite in the primary memory array 120 have two memory states, i.e., high resistance reset state and low resistance set state, the voltage difference between the sensing signal SSE and the reference signal SRE can be respectively given as follows:ΔVreset≡Vsense−Vreference=Iread1×Rreset−Iread2×(Rreset∥Rset)  (1),ΔVset≡Vsense−Vreference=Iread1×Rset−Iread2×(Rreset∥Rset)  (2),
wherein Iread1 is the read current applied to the primary memory array, Iread2 is the read current applied to the reference memory array, Rset is the resistance when the memory unit is in the set stste, and Rreset is the resistance when the memory unit is in the reset state. In order to make sure that the reference signal is approximate to the average of two sensing signals of reset state and set atate, the magnitude of the read current Iread2 is usually twice the magnitude of the read current Iread1. Thus, the equations (1) and (2) can be written as follows:|ΔVreset|=|Vsense−Vreference|=Iread1×[Rreset−2(Rreset∥Rset)]  (3),|ΔVset|=|Vsense−Vreference|=Iread1×[2(Rreset∥Rset)−Rset]  (4).
Since the resistance Rreset is much larger than the resistance Rset, the |ΔVreset| is large enough to be determined. However, the |ΔVset| is relatively small such that the reference signal is more unreliable and a sensing error may occur.